• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to an artificial neuron (1) comprising: - a so-called membrane capacitance (Cm), - a feedback-type pulsed circuit comprising: o a connected series and connected PMOS (8) and NMOS (7) transistor transistor; by a mid-point (9) to the membrane capacitance (Cm), o At least one so-called delay capacitance (Cna, Ck) between the gate and the source of one of the transistors (7, 8) of the bridge of generating a conduction / blocking time lag between the transistors of said bridge, o At least two CMOS inverters (5, 6, 10, 11, 12) between the membrane capacitance (Cm) and the gates of the transistors of said bridge so as to causing the transistors (7) and (8) of the bridge to change state as a function of the voltage of the membrane capacitance (Cm) and allow the pulse circuit to generate at least one pulse when the voltage of the membrane capacitor ( Cm) crosses a predefined threshold, with charge of the membrane capacitance (Cm) by one of the transistors (8) the bridge and discharge by the other transistor (7), the shape of the pulse being related to said time shift.
    公开号:FR3050050A1
    申请号:FR1653175
    申请日:2016-04-11
    公开日:2017-10-13
    发明作者:Alain Cappy；Francois Danneville；Virginie Hoel；Christophe Loyez
    申请人:De Lille 1, University of；Centre National de la Recherche Scientifique CNRS；Universite Lille 1 Sciences et Technologies；
    IPC主号:
    专利说明:

    ARTIFICIAL NEURONE
    The present invention relates to a circuit with low energy consumption, which can reproduce certain electrical properties of a biological neuron, and used especially in bioinspired architectures.
    After nearly forty years of exponential growth, commonly known as Moore's Law, the performance of information processing systems has begun to saturate due to excessive power dissipation. The combination of recent advances in neuroscience and the manufacture of nanodevices suggests the possibility of designing and manufacturing radically new architectures with energy efficiencies that are several orders of magnitude higher than current systems. These bioinspired or neuromorphic architectures reflect the operating principles currently known to the brain. They are made up of artificial neurons and synapses and they make it possible to perform functions such as associative memories, classifiers or function approximators.
    It is all the more important to design neuron circuits with the fewest transistors and consuming as little energy as these circuits are intended to be integrated into VLSI neural networks made up of several thousand neurons.
    Software approaches for bioinspired architectures based on brain simulation on a processor have been proposed, such as IBM's "Synapse" chip.
    Material approaches of bioinspired architectures have also been proposed, such as US Pat. No. 6,242,988 B1 using a positive feedback ('positive feedback') for the rapid generation of pulses, and the application EP 2 819 068 A2 implementing an artificial neuron comprising a resistive memory.
    More or less complex circuits, such as that described in the article by N.Qiao et al, Frontiers in Neuroscience, vol 9 article 141, 2015, reproduce in a CMOS technology the behavior of neurons, most often using the concept of 'log-domain circuits' or 'current mirror'.
    One of the most recognized biological membrane models in computational neuroscience is the Morris-Lecar model. This model was derived from measurements of electrical activity of a giant barnacle muscle fiber and described in an article published in Biophysics Journal, vol 35, 1981. Although based on a system of nonlinear differential equations reduced to only two variables (unlike other more complex four-variable models such as the Hodgkin-Huxley model), the Morris-Lecar model remains close to biology and can reproduce different pulse dynamics. The mathematical description of this model is inspired by the experimental observations of the ionic currents crossing the membrane of the muscular fiber.
    There are several known circuits reproducing the electrical properties of the Morris-Lecar cell membrane model as described in the article by R. Behdad et al., Published in IEEE Transactions on Neural Networks and Learning Systems, Vol 26, 2015. In this article, the ionic currents represented in the Morris-Lecar model are those of calcium and potassium, and the ohmic losses across the membrane are also modeled.
    In order to model a neuron, it is possible to replace calcium in this model with sodium. There, the different ion channels open or close which produces the electrical activity of the neuron. When, for example, external excitation is applied depolarizing the neuron membrane to a less negative potential, the rapid opening of the sodium (or calcium) channels produces a rapid increase in the neuron membrane potential, while that the opening of the potassium channels, slower, repolarizes the membrane of the neuron towards the negative resting voltage. This mechanism of activation / deactivation of the neuron produces pulses, also called action potentials ('spikes' in English).
    The circuit object of the R. Behdad article is broken down into several parts, corresponding to the different ionic currents, where each of the parts comprises discrete and active components, in particular transconductance operational amplifiers, which complicates the circuit.
    To date, there are no known devices or circuits satisfying the following constraints in a completely satisfactory manner: - A great simplicity of implementation resulting in a small area for integration on a very large scale. - a wide speed-power performance adjustment range (several parameters to define the speed-energy dissipated torque depending on the application), - using an existing CMOS industrial technology, - operating at very low voltage (supply voltage not exceeding - ^ Z-100mY) for a very low consumption, - having voltages compatible with a direct interface with the living, - which can have an energy efficiency of less than 1 £ I / pulse, ie several orders of magnitude lower than the value of the energy efficiency of a biological neuron, which can be stable or oscillating without excitation current, which can reproduce the generation of the pulses, their unmitigated propagation and the interconnections between neurons by means of synapses, - able to operate at a higher frequency than in the living to reduce the number of devices for the same computing power, which can faithfully reproduce the waveform in terms of time scale and amplitude of the action potential of the biological neurons, and which can reproduce the typical evolution of the frequency response of the action potential of a biological neuron as a function of the value of the excitation current. The aim of the invention is to propose an artificial neuron capable of responding to all or part of these constraints, and it achieves this, according to one of its aspects, thanks to an artificial neuron comprising:
    A so-called membrane capacity.
    A feedback pulse circuit comprising: A PMOS and NMOS transistor bridge in series and connected by a midpoint to the membrane capacitance. ο At least one so-called delay capacitance between the gate and the source of one of the transistors of the bridge so as to generate a conduction / blocking time delay between the transistors of said bridge, O At least two CMOS inverters between the membrane capacitor and the gates of the transistors of said bridge so as to cause the bridge transistors to change state depending on the voltage of the membrane capacitance and to allow the pulse circuit to generate at least one pulse when the voltage of the membrane capacitance crosses a predefined threshold, with loading of the membrane capacitance by one of the transistors of the bridge and discharge by the other transistor, the shape of the pulse being related to said time offset. The invention allows, if desired, to use a reduced number of transistors, thus limiting the area occupied by the circuit. An example of a complete circuit made in TSMC 65nm technology according to the invention occupies no more than 10 pm of surface whereas the soma of a biological neuron can be likened to a sphere of 1 to 50 μm in diameter depending on the type of neuron , the axon being able to reach millimeters, even centimeters, of length. The invention makes it possible to use transistors that can operate below the threshold in standard CMOS technology, and to use at least one inverter whose transistors operate below the threshold as a voltage gain stage. The operation of the transistors below the threshold corresponds to the existence of a drain-source current varying exponentially with the gate control voltage in the so-called weak inversion region of the transistor ('weak-inversion region' or 'subthreshold region' in English) where the gate-source voltage is below the threshold voltage for which the inversion zone appears (creation of a conduction channel between the drain and the source). The invention also allows the use of low capacitances for the membrane capacitance in particular of a value of less than 30 μF, in particular less than 10 μF, preferably of between 2 μF and 5 μF, whereas the membrane capacities in biology are of order of one or more hundreds of pF. The invention makes it possible to produce circuits having the advantage of dissipating a low energy per generated pulse, in particular of value less than 3.5 / / pulse, preferably lying between λ / 1 / pulse and 3.2 π / pulse, better than 0.5. fJ / pulse, while in biology the pulse energy generated is generally between 1 and 100 pJ. The energy dissipated by the artificial neuron according to the invention can be reduced in real operation by 1 to 2 orders of magnitude compared to existing artificial neural circuits.
    Thanks to the invention, it is possible to have a relatively fast operation of the neural circuit, for example at a frequency of the order of 100 kHz or more, while the frequency of the living does not exceed a few tens of Hz.
    Preferably, the artificial neuron comprises an input called external synaptic excitation current, the membrane capacity integrating this input current.
    The artificial neuron may have a resistance mounted in parallel with the membrane capacitance, increasing the charge / discharge times thereof, by analogy with the membrane leakage currents in the biological neuron. This leak resistance may consist of a resistor or a transistor operating in dipole.
    According to an advantageous embodiment, the charge of the membrane capacitance is ensured by the PMOS transistor of the bridge and its discharge by the NMOS transistor. In this case, the delay capacitance connected to the PMOS transistor is smaller than the delay capacitor connected to the NMOS transistor, and is preferably zero. The delay capacitance connected to the NMOS transistor is preferably greater than the membrane capacitance. This embodiment is close to the biological functioning of the neuron where the sodium / calcium channels (represented by analogy by the PMOS transistor of the bridge) are faster than the potassium channels (represented by analogy by the NMOS transistor of the bridge).
    The delay capacitance can be provided either by a physical component that is connected between the gate of the associated transistor and a corresponding terminal of the supply voltage, or by the single parasitic capacitance existing between the gate and the source of said transistor.
    According to an advantageous embodiment, the artificial neuron comprises two cascaded CMOS inverters, the input of the first inverter being connected to the membrane capacitor and its output to the input of the second inverter and to the gate of one of the transistors. the output of the second inverter being connected to the gate of the other transistor.
    The role of these inverters, each of which may consist of two transistors, is the shaping and voltage amplification of the signals used to control the transistors of the bridge. We can talk about positive feedback ('positive feedback').
    In a variant, the artificial neuron comprises two cascaded CMOS inverters, the input of the first inverter being connected to the membrane capacitor and its output to the input of the second inverter, the output of the second inverter being connected to the gate of the first inverter. one of the transistors of said bridge, and a third CMOS inverter whose input is connected to the membrane capacitance and the output to the gate of the other transistor of said bridge. The addition of the third inverter makes it possible to independently optimize the controls of the transistors of the bridge, by independently adjusting the threshold voltages of the inverters. The adjustment of the voltage gain and threshold voltages of the inverters influences the operation of the artificial neuron.
    Preferably, the threshold voltage of the neuron that produces the action potential is the threshold voltage of the inverter supplying the PMOS transistor of the bridge. The number of inverters used can be defined according to objectives of speed or energy consumption.
    Preferably, the threshold voltage of at least one of the CMOS inverters is different from OV, especially between -50mV and + 50mV.
    According to an advantageous characteristic of the invention, the artificial neuron operates in stable mode and the PMOS and NMOS transistors of said bridge have different conductance values, preferably in a ratio of at least 2, in particular from 2 to 7, for example from 5 to 7. The stable mode corresponds by analogy to that of the functioning of the neurons of the brain. In stable mode, to be able to generate pulses, the neuron must receive a nonzero external excitation current whose value depends on the degree of stability. Indeed, the greater the ratio of the conductances of the transistors of the bridge, the greater the stability, the greater the minimum intensity of the excitation current needed to disturb the stability is important.
    According to another advantageous characteristic of the invention, the artificial neuron operates in relaxation oscillator mode and the PMOS and NMOS transistors of said bridge may have relatively close conductance values, preferably in a ratio of 0.5 to 3, better still 0.8 to 1.2, even better of about 1.
    The relaxation oscillator mode corresponds, by analogy, to that of the operation of certain neurons of the spinal cord or of the cardiac cells. In relaxation oscillator mode, the neuron is unstable and generates pulses without external excitation current. In such a case, external synaptic excitation input is not necessary.
    According to the invention, the pulse circuit is powered by a power supply where Vd> Vs. The difference (Vd-Vs) is preferably fixed so that each inverter has a voltage gain greater than or equal to 2, in particular with a power supply such that (Vd-Vs)> = 100 mV, preferably (Vd-Vs)> = 120 mV. Generally, the voltage Vs is negative and between -200 mV and 0 mV, and the voltage Vd is positive and between 0 mV and +200 mV; for low energy operation, the negative voltage is preferably between -100 mV and -50 mV and the positive voltage between +50 and +100 mV; the negative voltage is in particular between -100 mV and -70 mV and the positive voltage between +70 and +100 mV for applications compatible with biology. The amplitude of the action potentials is preferably between 40 mV and 200 mV. The invention is not limited to a particular manufacturing technology of the neuron. According to an advantageous embodiment, the transistors of said bridge are made in a FD-SOI technology using the possibility of control by the substrate ('backgating' in English). The maximum current of the transistors is then controlled by a voltage applied to a substrate electrode called 'backgate'. This backgate voltage, by modifying the maximum current values of the transistors of the bridge, makes it possible to modify the frequency of the action potentials and the average power dissipated, the energy efficiency (energy dissipated by pulse) not being modified in such a way that sensitive.
    The artificial neuron can operate in a so-called burst mode, emitting pulses of pulses at regular intervals, by means of an excitation circuit integrating the membrane potential and re-injecting into the membrane capacitance a current resulting from this integration.
    The burst mode can also be obtained without external excitation current in the case where the neuron is unstable.
    The burst mode of the artificial neuron is particularly interesting for deep brain stimulation, useful in the treatment of neurological disorders such as Parkinson's disease.
    The artificial neuron can work by implementing stochastic resonance. The stochastic resonance phenomenon is a non-linear effect in which a random signal, especially a noise, promotes the transmission of a useful signal. This effect can take various forms, depending on the types considered for the noise, the useful signal, the non-linear transmission system, and the performance measurement which is improved by addition of noise.
    In this case, the artificial neuron receives an external excitation composed of two different currents: a periodic current of insufficient amplitude to generate action potentials and a random noise current. According to another of its aspects, the subject of the invention is also a neural network comprising a plurality of artificial neurons according to the invention as defined above, in which at least two artificial neurons, called pre-neuron and post-neuron neurones, are used. , are connected together by a synaptic circuit.
    Preferably, the synaptic circuit having two inputs comprises two transistors connected in series by their drains, at least one of said transistors being of NMOS type controlled by a gate potential corresponding to the first input of the synaptic circuit, the gate of the second transistor corresponding to the second input of the synaptic circuit, the output of the synaptic circuit corresponding to the source of the NMOS transistor being connected to the output potential of the post-neuron.
    There are two types of synapses: excitatory and inhibitory.
    Excitatory synapses, favoring the creation of an action potential by the post-neuron, depolarize the membrane of the post-neuron and have a role similar to that of the sodium channels. Their action can be simulated by a PMOS transistor connected to the positive terminal of the supply voltage.
    Inhibitory synapses, which disadvantage the creation of an action potential by the post-neuron, hyper-polarize the post-neuron membrane and have a role similar to that of the potassium channels. Their action can be simulated by an NMOS transistor connected to the negative terminal of the supply voltage.
    The synaptic circuit may correspond to an excitatory synapse where the second input of the synaptic circuit is connected to the output of an inverter having as input the membrane potential of the pre-neuron, in particular to the gate of the PMOS transistor of the pre-neuron bridge. .
    The synaptic circuit may also correspond to an inhibitory synapse where the second input of the synaptic circuit can be connected to the output of two inverters in series, the input of the first of which is subjected to the membrane potential of the pre-neuron.
    The second input of the synaptic circuit in the case of an inhibitory synapse can be connected to the gate of the NMOS transistor of the pre-neuron bridge. Another subject of the invention, according to another of its aspects, is an information processing method, in which a neural network as defined above is used for image processing, video processing or facial recognition. , for exemple.
    Preferably, an intrinsic thermal noise of the artificial neuron is used to maintain information within the neural network after learning.
    According to an advantageous embodiment, multiple action potentials at very high frequency are applied to the input of an integrator circuit whose output is connected to the first input of an excitatory synapse as defined above.
    Preferably, the integrating circuit comprises an NMOS transistor whose source, corresponding to the output of the integrator circuit, is connected to a capacitor, the gate and the drain of said transistor being connected together and corresponding to the input of the integrator circuit.
    It is also possible to operate the artificial neuron in burst mode by coupling it to a second low-frequency oscillating neuron via two synapses, one exciter from the first to the second neuron, and the other inhibitory to the second neuron. second to the first neuron.
    Preferably, the membrane and delay capabilities of the second neuron are at least 100 times greater than those of the first neuron.
    For example, the membrane capacity and delay values of the second neuron are O.lpF and IpF respectively, and those of the first neuron are respectively IfF and lOfF. According to another of its aspects, the subject of the invention is also an artificial spinal locomotive network ('Central Pattern Generator'), comprising at least two artificial neurons according to the invention and an inhibitory synapse as defined above. for the generation or regeneration of locomotor activity in living beings or for robotics, for example. The spinal locomotor network in the living is a network of neurons housed in the spinal cord.
    According to an advantageous embodiment, the artificial spinal locomotor network comprises a pre-neuron operating in burst mode and a post-neuron operating in oscillating mode, associated by an inhibitory synapse.
    According to another advantageous embodiment, the artificial spinal musculoskeletal network comprises two artificial neurons, both operating either in oscillating mode or in burst mode, and mutually coupled by two inhibitory synapses whose synaptic weights are equal or otherwise, so as to that each of the neurons is both pre and post-neuron. Synaptic weight is defined as the ratio of the post-synaptic potential amplitude (EPSP for Excitatory Post Synaptic Potential or IPSP for Inhibitory Post Synaptic Potential) to the amplitude of the pre-synaptic signal. that is, the action potential of the pre-neuron.
    The term "capacitance" can refer to both a capacitor as a component and its electrical capacitance as a physical variable, measured in Farads (F).
    The "membrane potential" refers to the terminal potential of the membrane capacitor connected to the mid-point of the transistor bridge. The invention will be better understood on reading the following description of non-limiting examples of implementation thereof, and on examining the appended drawing, in which: FIG. 1 schematically represents an artificial neuron according to a first embodiment of the invention, FIG. 2 is a view similar to FIG. 1 of an artificial neuron according to a second embodiment of the invention, FIG. 3 represents a digital simulation circuit. according to the second embodiment, FIGS. 4a and 4b illustrate the waveforms of the potentials and currents obtained by simulating the circuit of FIG. 3; FIG. 4c illustrates the waveforms of the membrane potential and currents of the channels; Ionic cells obtained by simulation of a biological neuron model. FIG. 5 represents a digital simulation circuit according to a third embodiment of the invention, FIG. 6 illustrates the waveforms of the potentials obtained by the digital simulation of the circuit of FIG. 5, FIG. 7 schematically represents an artificial neuron according to a fourth embodiment of the invention, FIGS. 8a to 8g represent results obtained by simulating a circuit according to FIG. 7, FIG. 9 schematically represents an artificial neuron according to a fifth embodiment of FIG. embodiment of the invention, FIG. 10 illustrates the input-output characteristic of an inverter under the threshold as a function of the ratio of the maximum drain currents of its transistors N and P, FIGS. 11a and 11b represent results obtained by the simulation digital circuit of a neuron circuit according to the invention, using the possibility of control by the substrate,
    FIG. 11c illustrates a digital simulation circuit of an artificial neuron highlighting the stochastic resonance phenomenon,
    FIG. 11d shows waveforms of excitation currents and membrane potential in the case of stochastic resonance, FIG. 12 schematically illustrates a portion of a neural network using an artificial neuron according to FIG. FIG. 13 schematically represents an interconnection of two neurons according to the invention by means of a synaptic circuit, FIG. 14 illustrates a digital simulation circuit of the interconnection of FIG. 13 in the case of an exciter synapse, FIG. 15 represents results obtained by the numerical simulation of the circuit of FIG. 14, FIG. 16 illustrates a digital simulation circuit similar to that of FIG. 14 in the case of an inhibitory synapse, FIG. represents results obtained by the digital simulation of the circuit of FIG. 16, FIG. 18 schematically illustrates a circuit using thermal noise e of the neuron to maintain the synaptic weight of an excitatory synapse, FIG. 19 represents the synaptic weight curves obtained by simulating the circuit of FIG. 18, with and without noise injection, FIG. 20 diagrammatically illustrates a neuron. FIG. 21 illustrates a Spice digital simulation scheme for the circuit of FIG. 20, FIGS. 22a and 22b show bursts of pulses obtained at the output of FIG. neuron with and without external excitation current respectively, FIG. 22c represents an artificial neural network consisting of two neurons coupled by two synapses, allowing one of the neurons to emit pulses of pulses, and FIG. results obtained by the numerical simulation of the circuit shown schematically in Figure 22c. FIG. 23 schematically illustrates an artificial spinal locomotor network consisting of two neurons and an inhibitory synapse, FIG. 24 represents results obtained by numerical simulation of the circuit of FIG. 23, FIG. 25 schematizes an artificial spinal locomotor network constituted of two neurons and two inhibitory synapses, FIGS. 26a and 26b illustrate results obtained by the numerical simulation of the circuit schematized in FIG.
    FIG. 1 shows the diagram of an artificial neuron 1 according to a first exemplary embodiment of the invention, with two inverters 5 and 6 connected in cascade, the output of the first being connected to the input of the second. The output of the first inverter 5 is connected to the gate of a PMOS transistor 8. The output of the second inverter is connected to the gate of an NMOS transistor 7.
    In FIG. 1, the transistors 7 and 8 are electrically connected in series and form a bridge between the supply voltages Vs and Vd.
    The mid-point 9, defining the connection of the drains of the bridge transistors, is connected to a terminal of a membrane capacitance Cm. The other terminal of the membrane capacitance Cm is connected to the ground OV. Otherwise, alternatively, this terminal can be connected to either Vs or Vd.
    In this example, we have Vs = <0 and Vd> = 0.
    A capacitor Ck is connected between Vs and the gate of the NMOS transistor 7. The terminal of the capacitor Ck connected to Vs may otherwise be connected to ground.
    A capacitance Cna is connected between Vd and the gate of the PMOS transistor 8. The terminal of the capacitor Cna connected to Vd may otherwise be connected to ground. lex denotes the external excitation current, for example originating from the synapses (not shown in FIG. 1).
    When the membrane potential Cm reaches the threshold voltage of the first inverter 5, a corresponding potential is then transmitted after a first inversion by the inverter 5 to the gate of the PMOS transistor 8, activating the latter after a delay defined by the capacitance Cna. . Thus, the membrane capacitance Cm is charged by the PMOS open conduction channel. This charge corresponds to the rising edge of the output action potential.
    When the threshold voltage of the second inverter 6 is reached, a corresponding potential is transmitted to the gate of the NMOS transistor 7, activating the latter after a delay defined by the delay capacitance Ck, which is in the example considered longer than the PMOS activation time, due to the choice of Ck> Cna. Thus, after having had time to charge, the membrane capacitance Cm begins to discharge at the opening of the NMOS conduction channel. This discharge corresponds to the falling edge of the output action potential.
    The supply voltages Vd and Vs are here the respective equivalents of the Nernst potentials of sodium and potassium by analogy with biology.
    The PMOS transistors 8 and NMOS 7 of the bridge respectively represent the sodium and potassium channels.
    The delay capacities Cna and Ck represent the time constants required to open the sodium and potassium channels respectively, as suggested by the Morris-Lecar model discussed above. Generally, and in accordance with the biology, the K channels are slower than the Na channels, resulting in Ck> Cna. In addition, in the example considered, the conductance of the NMOS transistor 7 of the bridge is greater than that of the PMOS transistor 8, which induces a rest potential of the membrane close to Vs, when the excitation current lex is zero .
    The capacity Cna can be equal to 0, as illustrated in FIG.
    FIG. 3 shows a digital simulation circuit realized with the Spice analog circuit simulator according to the example of FIG. 2.
    Transistors 8 and 7 of the bridge respectively correspond to transistors denoted M3 and M6 in FIG. 3, having a gate width equal to 0.6 μm. The inverter 5 consists of the two transistors M2 and M5, having a gate width equal to 0.3 pm. The inverter 6 consists of the two transistors M1 and M4, having gate widths equal to 0.3 pm and O.OSpm respectively.
    The gate length of the transistors is equal to 22 nm. The negative supply voltage is -100mV and the positive voltage is + 100mV.
    The capacities Ck and Cm are equal to 50fF and 10fF respectively.
    The external excitation current is constant, equal to 30pA.
    FIG. 4a represents the waveforms of the membrane potentials Vmem and the gate voltages Vna of the PMOS transistor 8 and gate Vk of the NMOS transistor 7.
    FIG. 4b represents, in addition to the membrane potential Vmem, the waveforms of the drain currents Id (M3) of the transistor 8 and Is (M6) of the drain of the transistor 7 of the circuit of FIG.
    These membrane potential waveforms and ionic current waveforms are similar to those encountered in the living as shown in FIG. 4c, where waveforms obtained by simulation on the Matlab® digital computing tool, Wei's biological neuron model (Y. Wei et al., The Journal of Neuroscience, August 27, 2014), where Ina and Ik represent the curves of the sodium and potassium currents respectively.
    A qualitative agreement of the waveforms between Figures 4b and 4c can be observed.
    In a variant where Ck <Cna and where the PMOS transistor of the bridge is more conductive than the NMOS transistor, the resting potential of the membrane is close to Vd and the outputs of the two inverters shown in Figure 1 are modified so that the output of the first inverter is connected to the gate of the NMOS transistor and the output of the second inverter is connected to the gate of the PMOS transistor.
    A Spice digital simulation circuit according to this third embodiment of the invention is illustrated in FIG.
    Figure 6 shows the waveforms obtained, and it is observed that the pulses are inverted with respect to those of Figure 4a.
    FIG. 7 schematically shows a neural circuit according to another exemplary embodiment of the invention, which differs from that of FIG. 2 in the presence of a leakage resistor Rf in parallel with the membrane capacitance Cm, by analogy with leaks across the biological membrane. It is still possible to eliminate this leakage resistance by adequate sizing of the transistors of the bridge so as to make the NMOS transistor much more conductive than the PMOS transistor.
    The Spice numerical simulation of this example was performed with the STM 28nm FD-SOI component library.
    The supply voltages Vs = -60mV and Vd = 60mV in this example make it possible to reach a peak-to-peak amplitude of 100mV. It is possible to obtain pulses for lower supply voltages, but the peak-to-peak amplitude of 100mV is then no longer reached.
    If the gate widths of the bridge transistors are equal, the PMOS transistor has a lower drain current than that of the NMOS transistor. As a result, the gate width of the PMOS transistor is preferably adjusted so as to balance these current values, the gate width of the NMOS transistor being, for example, equal to 80 nm and that of the PMOS to 450 nm.
    Figure 8a illustrates the membrane potential waveform in the case where Ck = 50 fF and Cm = 5 fF. 20 pulses of peak-to-peak amplitude of 100 mV are observed over a period of 1 ms.
    Figure 8b shows the waveform of the membrane potential in the case where Ck = 10 fF and Cm = 1 fF. There is an increase in the frequency of the pulses for the same duration of simulation.
    Figure 8c illustrates the lex cranial excitation current and the Vmem membrane potential. It is observed that the neuron reacts to the excitation.
    FIG. 8d represents the curve of variation of the frequency of the pulses as a function of the amplitude of the excitation current Lx.
    These results demonstrate that the excitation current Lx and the values of the capacitances Ck and Cm influence the frequency of the pulses, which proves the flexibility of the neural circuit in the sense that these different parameters can be used for the optimization of the pulses. exit.
    For Figures 8e and 8f, the value of Ck is set at 50 fF and Cm is varied from 2 fF to 50 fF.
    FIG. 8e represents the curve A of variation of the peak-to-peak amplitude of the membrane potential as well as the curve F of variation of the frequency of the pulses as a function of the capacitance Cm. There is a decrease in the amplitude and the frequency of the pulses with the increase of the value of the capacitance Cm.
    FIG. 8f represents, in addition to the curve F of variation of the frequency of the pulses, the curve R of evolution of the energy efficiency by pulse.
    It is observed that the energy consumed per pulse evolves very little (from 1.1 to 3.2 fl / pulse), in a quasi-linear manner, in the range [2 fF, 50 fF] of variation of Cm.
    FIG. 8g illustrates the variation of the frequency of the pulses (curve F) and of the energy efficiency per pulse (curve R) as a function of the capacitance Ck, the capacitance Cm being fixed at 2fF.
    The curves of Figures 8f and 8g have the same pace. It is also observed in FIG. 8g that the frequency of the pulses increases for low values of the capacitance Ck, and that the energy efficiency seems to be directly proportional to Ck, the value of Cm being constant.
    It can be seen that it is possible to obtain very low energy efficiency values, which can equal 0.3 fj per pulse for Ck = 5 fF and Cm = 2 fF.
    FIG. 9 schematically shows a neuron according to another exemplary embodiment of the invention, which differs from that of FIG. 2 by the addition of a third inverter 12, the first inverter 10 transmitting the output potential after reversal to the gate of the PMOS transistor 8 of the bridge and the two other inverters 11 and 12, connected in cascade, transmitting the output potential to the gate of the NMOS transistor 7.
    The inputs of the inverters 10 and 11 are connected to the midpoint 9 of the bridge and to the membrane capacitance, and the input of the inverter 12 is connected to the output of the inverter 11.
    With a few approximations, the output voltage Veut of an inverter under the threshold, powered symmetrically (Vs = - Vd), is given by:
    Vout = -Vd tanh [Wine / (nVt) + 0.5Ln (Ino / Ipo)]
    Vin is the input voltage of the inverter, Ino / Ipo is the ratio of the maximum currents of the NMOS and PMOS transistors, Vt is the thermal potential keT / q (ke being the Boltzmann constant, T the temperature and q load of 'an electron) and n is the coefficient of ideality, being greater than 1. The expression of Vont shows that the maximum voltage gain of the inverter is -Vd / (nVt) and that the threshold voltage is given by (-nVt / 2) Ln (Ino / Ipo).
    It is therefore possible to adjust the voltage gain provided by the inverters with the supply voltage, and the threshold voltage can be modified by a few nVt by adjusting the maximum currents of the NMOS and PMOS transistors (by modifying the gate width W of the transistors for example).
    FIG. 10 shows the input-output characteristic of an inverter under the threshold as a function of three different values of the ratio of the maximum currents of the NMOS and PMOS transistors: (Ino / Ipo) = 6 (curve Oi), (Lo / Ipo) = 1 (curve 02) and (Lo / Ipo) = 1/6 (curve 03).
    Transistors 7 and 8 of the bridge may be made of FD-SOI technology using the possibility of control by a substrate electrode. In this case, the maximum current of the transistors is not only controlled by their gate width W, but also by the substrate electrode. As a result, an action on the substrate voltage Vbb makes it possible to modify the temporal (capacitance charging capacity) and energy properties of the circuit.
    FIGS. 11a and 11b represent for the 28nm FD-SOI technology the influence of the substrate voltage on the maximum current of the transistor below the threshold and on the frequency of the pulses and the power dissipated.
    FIG. 11a illustrates the variation of the maximum current of a NMOS transistor under the threshold for different values of substrate voltage: Vbb = 0 (curve Y1), Vbb = - IV (curve Υ2) and Vbb = -2V (curve Y3) . These variations are given for a gate width W = 1.2pm and a drain-source voltage Vds = 0.1V.
    FIG. 1 Ib shows the impact of the substrate voltage on the pulse frequency in kHz at constant external excitation current (curve G), and on the total power dissipated in pW (curve H).
    FIG. 11c illustrates a digital simulation circuit of an artificial neuron exhibiting the stochastic resonance phenomenon. Neuron 1 is excited by two different sources of current: a periodic lexical current, sinusoidal in this case, of insufficient amplitude to generate action potentials and a random noise current Ib.
    FIG. 11d shows the waveforms of the two excitation currents and the membrane potential Vmem · When the periodic excitation current passes through a maximum, the added noise is sufficient to generate an action potential: the phenomenon of stochastic resonance.
    FIG. 20 illustrates an artificial neuron operating in burst mode where an adjoint excitation circuit 60 serves to integrate the membrane potential and to inject into the membrane capacitance an excitation current resulting from this integration, thus alternating continuously a regime of very fast pulses and a refractory regime.
    In order to obtain the burst mode of an artificial neuron according to the Morris-Lecar model, one possibility is that the relation between the lex excitation current and the membrane potential Vmem is governed by an equation of the type: diex / dt = s (Vo - Vmem (t - T), where S, Vq and T are constants to be defined according to the desired properties.
    This equation is that of an inductive circuit where the excitation current is proportional to the integral of the membrane potential.
    Indeed, when the resting membrane potential is close to Vs, the derivative of Iex / dt of the excitation current is positive. The excitation current increases and Vmem reaches the oscillation threshold. Oscillations increase the average value of the membrane potential, resulting in a negative dWdt current derivative and a decrease in the excitation current which then drops below a burst threshold.
    The principle of the burst mode of operation therefore consists in increasing, respectively decreasing, the excitation current when the membrane potential is below or respectively above a certain threshold.
    According to the constants ε, Vo and T, the burst mode can be obtained without excitation current Lx when the circuit is unstable.
    The excitation circuit 60 of FIG. 20 may comprise a follower amplifier, a delay line T and an integrating amplifier as illustrated in the Spice simulation scheme of FIG. 21. The source B2 on this diagram corresponds to a transconductance. to obtain the current to be reinjected into the membrane capacitance from the voltage Go to the output of the integrating amplifier.
    FIG. 22a shows burst pulses generated with an external excitation current step at 7pA. These burst pulses obtained without external excitation current are illustrated in FIG. 22b.
    An example of integration of an artificial neuron according to the invention in a neuromorphic system is illustrated schematically in FIG. 12. In a complete system of bioinspired processing of the information, called neural network 20, the artificial neuron 1 is connected to the input by a dendrite tree 50 which produces the lex excitation current. According to this current, the neuron produces an action potential which is transmitted to the output synapses 4 via an axon and a dendritic tree 51. The interconnection of two neurons, shown schematically in FIG. intermediate of a synaptic circuit 4.
    As the synapses are plastic (their effect varies according to the activities of the pre- and post-neurons), their plasticity is represented by a synaptic weight (modeled by the "weight" gate potential on a control NMOS transistor). This synaptic weight is assumed to be known, being defined by a learning sequence or generated by an ancillary circuit (Spike Timing Depends Plasticity circuit, for example).
    FIG. 14 represents a simulation circuit associating two neurons 1, 1 'by an excitatory synapse 2. The pre-neuron 1 is subjected to a constant lex excitation current, producing action potentials in a periodic manner, illustrated in FIG. FIG. 15 (Vmemi curve) · This membrane potential Vmemi attacks the synapse 2, after an inversion by the inverter 5, on the gate of the PMOS transistor M3 connected to the second input e2 of the synapse 2. The current delivered to the neuron 1 'is controlled by the potential Vi, variable in this case, applied to the "weight" gate of the NMOS transistor M16, and shown in FIG. 15. For the highest synaptic weights, an action potential Vu is generated by the post-neuron Γ at each pulse of the pre-neuron (Vmemr curve of Figure 15).
    Figure 16 represents the case of an inhibitory synapse 3 connecting the two neurons 1, Γ. The post-neuron 1 'is excited by a constant current 12 and produces pulses periodically. The pre-neuron 1 is excited by a constant current II only in the time interval between 1ms and 1.1ms, where it produces 5 action potentials (Vmemi curve of Figure 17). The inhibitory synapse 3 blocks the action potentials of the post-neuron in this time interval (Vmemr curve of Figure 17).
    Figures 18 and 19 illustrate the role of the intrinsic thermal noise of the neuron injected at the input of the circuit in the maintenance of synaptic weight.
    The case considered is that of the HF LTP (High Frequency Long Term Potentiation) where multiple very high frequency action potentials are applied to the input of an integrator whose output is connected to the input of the d a synaptic circuit.
    FIG. 18 represents an integrator circuit 15 comprising an NMOS transistor 16 and a capacitor 17. The output of the integrator is connected to the "weight" input of an exciter synapse 2. The HF pulses are obtained by the application of FIG. a constant lex current maintaining the excitation of the pre-neuron 1 during the first two milliseconds. Ib denotes in Figure 18 the synaptic noise current.
    Figure 19 shows the potential of synaptic weight (Vweight) with and without noise injection. It is observed that the synaptic weight increases (learning by integration) until the impulse stops at 2ms, resulting in a decrease in weight (by relaxation). The addition of noise (BR curve) reduces the relaxation phenomenon by keeping the high value of weight longer. The SBR curve represents the potential of synaptic weight in the absence of noise.
    Figure 22c schematically shows a neural network consisting of two neurons 1, 1 'coupled via two synapses, one exciter 2 from the first neuron 1 to the second 1' and the other inhibitor 3 of the second neuron 1 'to the first 1.
    Another possibility of obtaining the burst mode is to resort to this type of coupling between neurons 1, 1 ', having different oscillation frequencies. The first neuron 1, to oscillate at a higher frequency than the second neuron Γ, has values of Cmi membrane capacitance and Cki delay for example two orders of magnitude lower than those Cmr and Ckr of the second neuron Γ.
    A current step applied to the input of the first neuron generates a pulse train. These pulses generate an excitatory synaptic current at the entrance of the second neuron via the excitatory synapse 2, thus depolarizing the second neuron.
    When the second neuron depolarizes, it generates a train of pulses generating an inhibitory synaptic current at the entrance of the first neuron via the inhibitory synapse 3, thus hyperpolarizing the first neuron and stopping its pulses.
    Given the different oscillation frequencies of the two neurons, high frequency oscillations are obtained at the output of the first neuron, corresponding to bursts of pulses.
    Figure 22d illustrates these pulse bursts (Vout (l)) obtained following a current step of 1.5pA. It should be noted that the pulses are obtained for a minimum excitation current of 0.4pA. The frequency of the pulses observed increases with the amplitude of the current. To obtain the results of FIG. 22d, the supply voltages of the neurons and synapses are -O.IV and O.IV. The gate widths of the transistors of the inverters are 120 nm.
    FIG. 23 diagrammatically illustrates an artificial spinal locomotor network 21 consisting of two neurons, a pre-neuron 1 previously set in burst mode, connected to a post-neuron 1 'set in oscillating mode via an inhibitory synapse 3.
    Pre-neuron 1 drives the post-neuron 1 '. In fact, when it emits pulses, the pre-neuron 1 creates an inhibitory synaptic current at the input of the postneurone 1 'so as to prevent the latter from oscillating. During the hyperpolarization phase of pre-neuron 1 (absence of pulses), since the inhibitory synaptic current is not sufficient, the post-neuron 1 'oscillates normally as if it were isolated.
    FIG. 24 represents the waveforms at the output of the pre-neuron (Vni) and the post-neuron (Vni).
    FIG. 25 schematically illustrates a spinal locomotor network 21 consisting of two neurons 1, 1 'having identical characteristics, coupled together by means of two inhibitory synapses 3 of the same weight, so as to mutually inhibit each other. Two cases arise: either the two neurons are previously set in oscillating mode, or they are both previously set in burst mode.
    FIG. 26a represents the waveforms at the output of the two neurons 1, Γ, in the case where both are previously set in oscillating mode. We observe after 150ms that their oscillations occur alternately.
    FIG. 26b illustrates the waveforms at the output of the two neurons 1,1 ', in the case where both are previously set in burst mode. It is observed that the synchronization leading to the operation in alternating burst mode of the two neurons 1, 1 'is obtained after about 50 ms.
    The present invention can be used in at least two domains.
    The artificial neuron according to the invention can be used as basic brick in neuroinspired information processing systems, especially in image processing, video and facial recognition. In this case, the elements of the neural circuit will be optimized for a high speed and / or a very low dissipated power.
    Moreover, the neuron according to the invention can be used in biomedical applications as an artificial biological neuron (implant). In this case, the elements of the circuit are optimized to faithfully reproduce the action potential of the biological neurons.
    权利要求:
    Claims (35)
    [1" id="c-fr-0001]
    1. Artificial neuron (1; Γ) comprising: - a membrane capacitance (Cm), a feedback pulse circuit comprising: O a PMOS transistor bridge (8) and NMOS (7) in series and connected by a mid-point (9) at the membrane capacitance (Cm), at least one delayed capacitance (Cna, Ck) input the gate and the source of one of the transistors (7,8) of the bridge so as to generate a conduction / blocking time delay between the transistors of said bridge, O At least two CMOS inverters (5,6; 10,11,12) between the membrane capacitance (Cm) and the gates of the transistors of said bridge so as to bring the transistors (7, 8) of the bridge to change state depending on the voltage of the membrane capacitance (Cm) and allow the pulse circuit to generate at least one pulse when the voltage of the membrane capacitance (Cm) passes a predefined threshold, with charge of the membrane capacitance (Cm) by one of the transistors (8) of the bridge and discharge p by the other transistor (7), the shape of the pulse being related to said time decay.
    [2" id="c-fr-0002]
    2. Artificial neuron (1; 1 ') according to the preceding claim, comprising ime said input of external synaptic excitation (lex) current, the membrane capacity integrating this input current.
    [3" id="c-fr-0003]
    3. Artificial neuron (1; 1 ') according to claim 1 or 2, the charge of the membrane capacitance (Cm) being provided by the PMOS transistor (8) of the bridge and its discharge by the NMOS transistor (7).
    [4" id="c-fr-0004]
    4. Artificial neuron (1; 1 ') according to claim 3, the delay capacitance (Cna) connected to the PMOS transistor (8) being less than the delay capacitance (Ck) connected to the NMOS transistor (7), better being zero .
    [5" id="c-fr-0005]
    5. Artificial neuron (1; Γ) according to claim 4, the delay capacitance (Ck) connected to the NMOS transistor (7) being greater than the membrane capacitance (Cm).
    [6" id="c-fr-0006]
    6. Artificial neuron (1; 1 ') according to any one of the preceding claims, comprising two cascaded CMOS inverters (5, 6), the input of the first inverter (5) being connected to the membrane capacitor (Cm). and its output to the input of the second inverter (6) and the gate of one of the transistors (7; 8), the output of the second inverter (6) being connected to the gate of the other transistor (7; 8).
    [7" id="c-fr-0007]
    Artificial neuron (1; Γ) according to any one of claims 1 to 5, comprising two cascaded CMOS inverters (11, 12), the input of the first inverter (11) being connected to the membrane capacitance (Cm ) and its output to the input of the second inverter (12), the output of the second inverter (12) being connected to the gate of one of the transistors of said bridge, and a third CMOS inverter (10) dceit. the input is connected to the membrane capacitance (Cm) and the output to the gate of the other transistor of said bridge.
    [8" id="c-fr-0008]
    8. Artificial neuron (1; Γ) according to any one of the preceding claims, operating in stable mode, the PMOS transistors (8) and NMOS (7) of said bridge having different conductance values, preferably in a ratio of at least 2, in particular from 2 to 7, in particular from 5 to 7.
    [9" id="c-fr-0009]
    9. Artificial neuron (1; Γ) according to any one of claims 1 to 7, operating in relaxation oscillator mode, the PMOS transistors (8) and NMOS (7) of said bridge having close conductance values, preferably in a ratio equal to 1.
    [10" id="c-fr-0010]
    10. artificial neuron (1; 1 ') according to any one of the preceding claims, the pulse circuit being powered by a supply with the negative voltage (Vs) between -200 mV and 0 mV and the positive voltage (Vd) included between 0 mV and +200 mV, better the negative voltage (Vs) between -100 mV and -50 mV and the positive voltage (Vd) between +50 and +100 mV.
    [11" id="c-fr-0011]
    11. Artificial neuron (1; Γ) according to any one of the preceding claims, the amplitude of said at least one pulse is between 40 mV and 200 mV
    [12" id="c-fr-0012]
    12. Artificial neuron (1; 1 ') according to any one of the preceding claims, the difference (Vd-Vs) being set so that the voltage gain of each CMOS inverter is greater than or equal to 2, this difference being in particular greater than or equal to 100mV, better at 120mV.
    [13" id="c-fr-0013]
    13. Artificial neuron (1; Γ) according to any one of the preceding claims, the threshold voltage of at least one of the CMOS inverters being different from OV, especially between -50mV and + 50mV
    [14" id="c-fr-0014]
    14. Artificial neuron (1; Γ) according to any of the preceding claims, comprising a leakage resistor (Rf) in parallel with the membrane capacitance (Cm).
    [15" id="c-fr-0015]
    15. Artificial neuron (1; Γ) according to any one of the preceding claims, the transistors (7) and (8) of said bridge being made in a FD-SOI technology using the possibility of control by the substrate, to control the maximum current of the transistors (7,8) per substrate electrode.
    [16" id="c-fr-0016]
    16. Artificial neuron (1; 1 ') according to any one of the preceding claims, comprising an adjoint excitation circuit (60) integrating the membrane potential, and reinjecting a current resulting from this integration into the membrane capacity.
    [17" id="c-fr-0017]
    17. Artificial neuron (1; Γ) according to any one of the preceding claims, exploiting a stochastic resonance phenomenon by receiving an external excitation of two different currents: a periodic (lex) current of insufficient amplitude to generate action potentials and a random noise current (Ib).
    [18" id="c-fr-0018]
    18. Neural network (20), comprising a plurality of artificial neurons (1; Γ) as defined in any one of the preceding claims.
    [19" id="c-fr-0019]
    19. Neural network (20) according to the preceding claim, comprising at least two artificial neurons (1, 1 '), said pre-neuron (1) and post-neuron (Γ), connected together by a synaptic circuit (4).
    [20" id="c-fr-0020]
    20. Neural network (20) according to the preceding claim, the synaptic circuit (4) having two inputs and having two transistors (Ml 6, Ml 3) connected in series by their drains, at least one of said transistors being of NMOS type. (Ml6) controlled by xm gate potential (VI) corresponding to the first input (weight) of the synaptic circuit, the gate of the second transistor corresponding to the second input (e2) of the synaptic circuit, the output of the synaptic circuit corresponding to the source the NMOS transistor (M16) being connected to the output potential (Vmemi ') of the post-neuron (1').
    [21" id="c-fr-0021]
    21. Neural network (20) according to the preceding claim, the synaptic circuit (4) corresponding to an excitatriated synapse (2) where the second input (e2) of the synaptic circuit is connected to the output of an inverter (5) having input the membrane potential of the pre-neuron (1), in particular to the gate of the PMOS transistor (8) of the pre-neuron bridge (1).
    [22" id="c-fr-0022]
    22. neural network (20) according to claim 20, the synaptic circuit (4) corresponding to xme synapse inhibitory (3) where the second input (e2) of the synaptic circuit is connected to the output of two inverters in series whose input of the former is subject to the membrane potential of the pre-neuron (1).
    [23" id="c-fr-0023]
    23. The neural network (20) according to claim 20, the S3maptic circuit (4) corresponding to an inhibitory synapse (3) where the second input (e2) of the synaptic circuit is connected to the gate of the NMOS transistor (7) of the bridge. pre-neuron.
    [24" id="c-fr-0024]
    24. neural network (20) according to any one of claims 18 to 23, comprising two artificial neurons (1,1 '), including a first high frequency oscillating neuron (1) and a second oscillating neuron (Γ) at low frequency, the first neuron (1) operating in burst mode being coupled to the second neuron (Γ) via two synapses, one exciter (2) from the first (1) to the second neuron (1 '), and the other inhibitor (3) of the second (1 ') to the first neuron (1).
    [25" id="c-fr-0025]
    25. neural network (20) according to the preceding claim, the membrane capacitance (Cm) and delay (Ck, Cna) of the second neuron being at least 100 times greater than those of the first neuron.
    [26" id="c-fr-0026]
    26. Information processing method, in which a neural network (20) as defined in one of claims 18 to 23 is used.
    [27" id="c-fr-0027]
    27. Method according to the preceding claim, wherein an intrinsic thermal noise of the artificial neuron (1; Γ) is used to maintain information within the neural network (20) after learning.
    [28" id="c-fr-0028]
    28. The method according to the preceding claim, wherein multiple very high frequency action potentials are applied to the input of an integrator circuit (15) whose output is connected to the first input (weight) of an S3mapse. exciter (2).
    [29" id="c-fr-0029]
    29. Method according to the preceding claim, wherein the integrator circuit (15) comprises an NMOS transistor (16) whose source, corresponding to the output of the integrator circuit (15), is connected to a capacitor (17), the gate and the drain of said transistor (16) being connected together and corresponding to the input of the integrator circuit (15).
    [30" id="c-fr-0030]
    30. artificial spinal locomotor network (21), comprising at least two artificial neurons (1,1 ') according to any one of claims 1 to 17, said pre-neuron (1) and post-neuron (1'), and sjmapse inhibitory (3).
    [31" id="c-fr-0031]
    31. artificial spinal locomotor network (21) according to the preceding claim, the inhibitory synapse (3) having two synaptic inputs and comprising two transistors (Ml6, Ml3) connected in series by their drains, at least one of said transistors being of type NMOS (Ml6) controlled by a gate potential (VI) corresponding to the first synaptic input (wei t), the gate of the second transistor corresponding to the second synaptic input (e2) being connected to the output of two inverters in series of which the input of the first is subjected to the membrane potential of the pre-neuron (1), the output of the synapse corresponding to the source of the NMOS transistor (M1 6) being connected to the output potential (Vmemr) of the post-neuron (1 ') ·
    [32" id="c-fr-0032]
    32. The artificial spinal locomotor network (21) according to claim 30, the inhibitory synapse (3) having two synaptic inputs and comprising two transistors (Ml6, Ml 3) connected in series by their drains, at least one of said transistors being of t3q> e NMOS (Ml 6) controlled by a gate potential (VI) corresponding to the first synaptic input (weight), the gate of the second transistor corresponding to the second synaptic input (e2) being connected to the gate of the NMOS transistor ( 7) of the pre-neuron bridge (1), the output of the synapse corresponding to the source of the NMOS transistor (Ml6) being connected to the output potential (Vmemr) of the post-neuron (1 ') ·
    [33" id="c-fr-0033]
    33. The artificial spinal locomotor network (21) according to any of claims 30 to 32, comprising a pre-neuron operating in burst mode and a post-neuron operating in oscillating mode, associated by an inhibitory synapse (3).
    [34" id="c-fr-0034]
    34. Artificial locomotor network (21) according to any one of claims 30 to 32, comprising two artificial neurons (1,1 '), both operating in oscillating mode, and mutually coupled by two inhibitory synapses (3), so that each of the neurons is both pre and post-neuron.
    [35" id="c-fr-0035]
    The artificial spinal locomotor network (21) according to any one of claims 30 to 32, comprising two artificial neurons (Ι, Γ) both operating in burst mode, and mutually coupled by two inhibitory synapses (3), so that each of the neurons is both pre and post-neuron.
    类似技术:
    公开号 | 公开日 | 专利标题
    FR3050050A1|2017-10-13|ARTIFICIAL NEURONE
    Cruz-Albrecht et al.2012|Energy-efficient neuron, synapse and STDP integrated circuits
    Wu et al.2015|A CMOS spiking neuron for brain-inspired neural networks with resistive synapses and in situ learning
    EP2965269B1|2018-08-22|Artificial neuron and memristor
    KR20170008747A|2017-01-24|Update of classifier over common features
    Cantley et al.2012|Neural learning circuits utilizing nano-crystalline silicon transistors and memristors
    KR101793011B1|2017-11-02|Efficient hardware implementation of spiking networks
    KR102230784B1|2021-03-23|Synapse circuit for spike-timing dependent plasticity| operation and neuromorphic system
    Bofill-i-Petit et al.2004|Synchrony detection and amplification by silicon neurons with STDP synapses
    FR2977350A1|2013-01-04|NETWORK OF ARTIFICIAL NEURONS BASED ON COMPLEMENTARY MEMRISTIVE DEVICES
    US20120011091A1|2012-01-12|Methods and systems for cmos implementation of neuron synapse
    US10140573B2|2018-11-27|Neural network adaptation to current computational resources
    TW201329876A|2013-07-16|Method and apparatus for structural delay plasticity in spiking neural networks
    US10657440B2|2020-05-19|Optical synapse for neuromorphic networks
    KR20160084401A|2016-07-13|Implementing synaptic learning using replay in spiking neural networks
    Giulioni et al.2015|Real time unsupervised learning of visual stimuli in neuromorphic VLSI systems
    US9959499B2|2018-05-01|Methods and apparatus for implementation of group tags for neural models
    Afifi et al.2011|CMOL implementation of spiking neurons and spike‐timing dependent plasticity
    Liu2003|Analog VLSI circuits for short-term dynamic synapses
    Bofill et al.2001|Citcuits for VLSI implementation of temporally asymmetric Hebbian learning
    US8653867B1|2014-02-18|Pulse modulated neural integrator circuit and associated phase locked loop
    EP3794514A1|2021-03-24|Switched artificial synapse
    Huayaney et al.2016|A VLSI implementation of a calcium-based plasticity learning model
    Northmore et al.1996|Spike train processing by a silicon neuromorph: The role of sublinear summation in dendrites
    FR3089037A1|2020-05-29|NEURONAL CIRCUIT CAPABLE OF IMPLEMENTING SYNAPTIC LEARNING
    同族专利:
    公开号 | 公开日
    EP3443506A1|2019-02-20|
    IL262329A|2022-02-01|
    JP6906602B2|2021-07-21|
    US20190130258A1|2019-05-02|
    IL262329D0|2018-11-29|
    JP2019517085A|2019-06-20|
    CN109478249A|2019-03-15|
    FR3050050B1|2021-10-15|
    KR20180136476A|2018-12-24|
    WO2017178352A1|2017-10-19|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    WO2019081562A1|2017-10-25|2019-05-02|École Centrale De Lille|Optical sensor|
    FR3081073A1|2018-05-14|2019-11-15|Universite De Lille|ARTIFICIAL SYNAPSE SWITCHED|US6242988B1|1999-09-29|2001-06-05|Lucent Technologies Inc.|Spiking neuron circuit|
    CN101364594B|2007-08-09|2010-06-02|中国科学院半导体研究所|Silicon based single electron neure quantum circuit|
    US8275728B2|2009-11-05|2012-09-25|The United States Of America As Represented By The Secretary Of The Air Force|Neuromorphic computer|
    FR3007867B1|2013-06-26|2018-02-09|Commissariat A L'energie Atomique Et Aux Energies Alternatives|ARTIFICIAL NEURONE COMPRISING A RESISTIVE MEMORY|
    KR20150034900A|2013-09-26|2015-04-06|삼성전자주식회사|Synapse circuit for connecting neuron circuits, unit cell composing neuromorphic circuit, and neuromorphic circuit|
    CN105426957B|2015-11-06|2017-09-29|兰州理工大学|A kind of electrical activity of neurons simulator under electromagnetic radiation|JP6765686B2|2016-11-30|2020-10-07|国立研究開発法人科学技術振興機構|Neuron circuits, systems and switch circuits|
    FR3064383B1|2017-03-23|2019-11-15|Stmicroelectronics Sa|INTEGRATED ARTIFICIAL NEURONE DEVICE|
    US20180330227A1|2017-05-09|2018-11-15|International Business Machines Corporation|Stdp with synaptic fatigue for learning of spike-time-coded patterns in the presence of parallel rate-coding|
    CN108446762A|2018-03-30|2018-08-24|广西师范大学|A kind of hardware circuit of the analog pulse neuron based on MOS field-effect transistors and its application|
    KR102246807B1|2018-05-30|2021-04-30|서울대학교산학협력단|Artificial sensory nervous system device including artificial synapse|
    US10490273B1|2018-10-15|2019-11-26|International Business Machines Corporation|Linearly weight updatable CMOS synaptic array without cell location dependence|
    CN111523658B|2020-07-02|2020-12-15|南京优存科技有限公司|Double-bit memory cell and circuit structure of in-memory calculation thereof|
    CN112183738B|2020-10-09|2022-01-18|中国人民解放军陆军工程大学|Demonstration system for simulating multiple discharge modes of neuron|
    法律状态:
    2017-03-31| PLFP| Fee payment|Year of fee payment: 2 |
    2017-10-13| PLSC| Publication of the preliminary search report|Effective date: 20171013 |
    2018-03-30| PLFP| Fee payment|Year of fee payment: 3 |
    2019-04-29| PLFP| Fee payment|Year of fee payment: 4 |
    2020-04-30| PLFP| Fee payment|Year of fee payment: 5 |
    2021-04-29| PLFP| Fee payment|Year of fee payment: 6 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1653175A|FR3050050B1|2016-04-11|2016-04-11|ARTIFICIAL NEURONE|FR1653175A| FR3050050B1|2016-04-11|2016-04-11|ARTIFICIAL NEURONE|
    CN201780036378.9A| CN109478249A|2016-04-11|2017-04-07|Artificial neuron|
    KR1020187032579A| KR20180136476A|2016-04-11|2017-04-07|Artificial neuron|
    PCT/EP2017/058339| WO2017178352A1|2016-04-11|2017-04-07|Artificial neuron|
    EP17715186.7A| EP3443506A1|2016-04-11|2017-04-07|Artificial neuron|
    US16/092,649| US20190130258A1|2016-04-11|2017-04-07|Artificial neuron|
    JP2019503773A| JP6906602B2|2016-04-11|2017-04-07|Artificial neuron|
    IL262329A| IL262329A|2016-04-11|2018-10-11|Artificial neuron|
    [返回顶部]